Specifications

7-64 System Registers
Table 7-30 TLEPDERR Register Bit Definitions
Name Bit(s) Type Function
RSVD
Ctrl/P_HALT_ENA
HALT_ENA
INTIM_ENA
IP_ENA
IPL17_ENA
IPL16_ENA
IPL15_ENA
IPL14_ENA
DUART0_ENA
<31:9>
<8>
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
Reserved. Must be written as zeros.
Ctrl/P Halt Enable. Enables halt through ^P if
<TLSB_SECURE> of GBUS$MISCR is not set,
and if a ^P Halt interrupt is received from the
Gbus.
CPU Halt Enable. Enables halts by writes to
TLCNR<HALT> for this CPU.
Interval Timer Interrupt Enable. The inter-
val timer can be set to interrupt or to be polled. If
the timer is set to interrupt, the interrupts can be
directed to either CPU or to both.
Interprocessor Interrupt Enable. When set,
enables interprocessor interrupts to this register’s
associated CPU.
IPL17 Interrupt Enable. If set, IPL17 inter-
rupts from the I/O port or other TLSB I/O devices
are enabled to this register’s associated CPU.
IPL16 Interrupt Enable. If set, IPL16 inter-
rupts from the I/O port or other TLSB I/O devices
are enabled to this register’s associated CPU.
IPL15 Interrupt Enable. If set, IPL15 inter-
rupts from the I/O port or other TLSB I/O devices
are enabled to this register’s associated CPU.
IPL14 Interrupt Enable. If set, IPL14 inter-
rupts from the I/O port or other TLSB I/O devices
are enabled to this register’s associated CPU.
DUART0 Interrupt Enable. If set, enables
DUART interrupts from DUART0 to this regis-
ter’s associated CPU.