Specifications

System Registers 7-63
TLINTRMASK0–1—Interrupt Mask Registers
A
ddress
A
ccess
BB + 1100, BB + 1140
R/W
The TLINTRMASK0–1 registers are used to enable interrupts to
the CPUs. TLINTRMASK0 controls interrupts on CPU0 and TLIN-
TRMASK1 on CPU1.
31 9 43 08765 12
BXB-0770-93
Ctrl/P HALT ENA
HALT ENA
INTIM_ENA
IP_ENA
IPL17_ENA
IPL16_ENA
IPL15_ENA
IPL14_ENA
DUART0_ENA
RSVD
