Specifications

7-62 System Registers
TLEP_VMG—Voltage Margining Register
Table 7-29 TLEP_VMG Register Bit Definitions
A
ddress
A
ccess
BB + 15C0
R/W
The TLEP_VMG register is implemented in DIGA1. It drives the
voltage margining circuit on the CPU module to vary the 5 V and
3.3 V supplies. The otherwise unused (on DIGA1) interrupt lines
are used for this function. Any value written into this register is
cleared on reset.
31 3012
RSVD
BXB-0502V-93
3V - 5% 
3V + 5%
4
5V - 5%
5V + 5%
Name Bit(s) Type Function
RSVD
3 V -5%
3 V +5%
5 V -5%
5 V +5%
<31:4>
<3>
<2>
<1>
<0>
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
Reserved. Must be written as zeros.
Set 3.3 V Down 5%.
Set 3.3 V Up 5%.
Set 5 V Down 5%.
Set 5 V Up 5%.