Specifications

7-60 System Registers
Table 7-28 TLEPMERR Register Bit Definitions
Name Bit(s) Type Function
RSVD
RSTSTAT
D2DCPE3
D2DCPE2
D2DCPE1
<31:7>
<6>
<5>
<4>
<3>
R/W, 0
W1C, 0
W1C, 0
W1C, 0
W1C, 0
Reserved. Must be written as zeros.
Node Reset Status. When set, indicates that the
node was reset by writing 1 to TLCNR<NRST>.
DIGA to DIGA CSR Parity Error #3. Set when
DIGA3 detects a parity error on the DIGA to DIGA
CSR bus. This error can occur when a CSR in DIGA3 is
being written or read. This error can be detected on
either CSR data or CSR command/address informa-
tion, but only when DIGA3’s DCSR valid bit is as-
serted, or during a DIGA0 to DIGA3 data movement.
This error indicates that CSR data has been corrupted.
This is a hard error and causes a machine check.
DIGA to DIGA CSR Parity Error #2. Set when
DIGA2 detects a parity error on the DIGA to DIGA
CSR bus. This error can occur when a CSR in DIGA2
is being written or read. This error can be detected on
either CSR data or CSR command/address informa-
tion, but only when DIGA2’s DCSR valid bit is as-
serted, or during a DIGA0 to DIGA2 data movement.
This error indicates that CSR data has been corrupted.
This is a hard error and causes a machine check.
DIGA to DIGA CSR Parity Error #1. Set when
DIGA1 detects a parity error on the DIGA to DIGA
CSR bus. This error can occur when a CSR in DIGA1
is being written or read. This error can be detected on
either CSR data or CSR command/address informa-
tion, but only when DIGA1’s DCSR valid bit is as-
serted, or during a DIGA0 to DIGA1 data movement.
This error indicates that CSR data has been corrupted.
This is a hard error and causes a machine check.