Specifications

System Registers 7-59
TLEPMERR—MMG Error Register
A
ddress
A
ccess
BB + 1580
R/W
The TLEPMERR register contains CPU module error bits. These
bits are set as a result of errors detected in the MMG. This regis-
ter also contains the node reset status bit.
31 3012
RSVD
BXB-0502-93
D2DCPE3: DIGA to DIGA CSR Parity Error #3
D2DCPE2: DIGA to DIGA CSR Parity Error #2
D2DCPE1: DIGA to DIGA CSR Parity Error #1

A2MAPE1: ADG to MMG Address Parity Error #1
A2MAPE0: ADG to MMG Address Parity Error #0
4
6
5

D2MCPE: DIGA to MMG CSR Parity Error 

78

RSTSTAT 
