Specifications

System Registers 7-57
TLEPDERR—DIGA Error Register
A
ddress
A
ccess
BB + 1540
R/W
The TLEPDERR register contains CPU module error bits. These
bits are set as a result of errors detected in the MMG or any of the
DIGA chips. This register resides in DIGA0.
31 3012
RSVD
BXB-0503-93
GBTO: Gbus Timeout Error
D2DCPE0: DIGA to DIGA CSR Parity Error #0
A2DCPE: ADG to DIGA CSR Parity Error
