Specifications

System Registers 7-53
Table 7-25 TLMODCONFIG Register Bit Definitions (Continued)
NOTE: A write to the TLMODCONFIG register must be followed by a MEMB. The
acknowledge of this MEMB will be held off until the module is reconfig-
ured. The TLMODCONFIG register should only be written when
TLDIAG<FRIGN> is set.
Name Bit(s) Type Function
BQ_MAX_ENT
CQ_MAX_ENT
BCIDLETIM
RM_SIZE
LOCKOUT_EN
BCACHE_SIZE
CPU1_DIS
CPU0_DIS
<15:13>
<12:10>
<9:6>
<5>
<4>
<3:2>
<1>
<0>
R/W, 4
R/W, 4
R/W, F
R/W, F
R/W, 1
R/W, 0
R/W, 0
R/W, 0
Bus Queue Maximum Entries. Indicates the maxi-
mum number of bus queue entries supported. Not all
values are supported.
Cache Queue Maximum Entries. Indicates the
maximum number of cache queue entries supported.
Not all values are supported.
B-Cache Idle Time. Time that BC_IDLE must be as-
serted before fill data can be returned. Value indicates
the number of sysclock cycles. The default is set to the
highest value. Legal values are 2 to F. Set the value
to the desired number of cycles of BC_IDLE assertion
plus 2. (If 7 cycles of the BC_IDLE assertion are re-
quired, then set this field to 9.) The appropriate value
should be written here for optimum system perform-
ance.
Memory Channel Size. When set, the CPU module
sets Memory Channel threshold at five buffers; when
clear, threshold is three.
Lockout Enable. When set, enables lockouts. In-
itialized to 1.
B-Cache Size. Value is read by console from
GBUS$MISCR and loaded in this field. May also be
changed for prototype debug. Indicates B-cache sizes
as follows:
CPU1 Disable. Can be set to cause service requests
from the DECchip 21164 to be ignored.
CPU0 Disable. Can be set to cause service requests
from the DECchip 21164 to be ignored.
<BCACHE_SIZE> Cache Size per CPU
00
01
10
11
Reserved
4 Mbytes
16 Mbytes
Reserved