Specifications

System Registers 7-47
TLDIAG—Diagnostic Setup Register
Table 7-22 TLDIAG Register Bit Definitions
A
ddress
A
ccess
BB + 1000
R/W
The TLDIAG register is used to configure the module for the vari-
ous diagnostic modes required for a complete module-level self-
test. Only one diagnostic setup register is specified, shared be-
tween the two CPUs.
31 16 15 14 13 12 11 10 9 43 0876 12
RSVD
BXB-0500-93
GSLOW
QWVAL_EN: Quadword Valid Enable
ASSRT_FLT: Assert Fault
RSVD
FDE3: Force Data Error
FDE2: Force Data Error
FDE1: Force Data Error
FDE0: Force Data Error
FDBE: Force Double-Bit Error

DTCP: Dtag CPU
DTRD: Dtag Read
DTWR: Dtag Write
FRIGN: Force Ignore
RSVD
Name Bit(s) Type Function
RSVD
GSLOW
QWVAL_EN
<31:16>
<15>
<14>
R/W, 0
R/W, 0
R/W, 0
Reserved. Must be written as zeros.
Gbus Slow. When set, causes the Gbus clock to run at
TLSB_clk/12 instead of TLSB_clk/6.
Quadword Valid Enable. When set, enables the gen-
eration of quadword data valid bit to the bus, instead of
octaword data valid bits.