Specifications

System Registers 7-45
Table 7-20 CPU Module Registers
Mnemonic Name Address
Module Registers
TLDIAG
TLDTAGDATA
TLDTAGSTAT
TLMODCONFIG
TLCON00
TLCON0A
TLCON0B
TLCON0C
TLCON10
TLCON1A
TLCON1B
TLCON1C
TLCON01
TLCON11
TLEPAERR
TLEPDERR
TLEPMERR
TLEP_VMG
TLDMCMD
TLDMADRA
TLDMADRB
TLPM_CMD
TLPM_TOT_CYC
TLPM_EV5_LAT
TLPM_RD_LAT
TLPM_SYS_OWN
TLPM_CMD_SILO
TLPM_LOCK
TLPM_MB
TLPM_SD_TOTAL
TLPM_SD_ACKED
TLPM_RD_CSR
TLPM_RD
TLPM_RD_MOD
TLPM_RD_STC
TLPM_VICTIM
TLPM_WR_CSR
TLPM_WR
TLPM_WR_LOCK
TLPM_INVAL
TLPM_SET_SHRD
TLPM_RD_DIRTY
TLPM_ADR_SILO
Diagnostic Setup Register
DTag Data Register
DTag Status Register
CPU Module Configuration Register
Console Communications Register 0 for CPU0
DIGA Communications Test Register 0 for DIGA1
DIGA Communications Test Register 0 for DIGA2
DIGA Communications Test Register 0 for DIGA3
Console Communications Register 0 for CPU1
DIGA Communications Test Register 1 for DIGA1
DIGA Communications Test Register 1 for DIGA2
DIGA Communications Test Register 1 for DIGA3
Console Communications Register 1 for CPU0
Console Communications Register 1 for CPU1
ADG Error Register
DIGA Error Register
MMG Error Register
Voltage Margining Register
Data Mover Command Register
Data Mover Source Address Register
Data Mover Destination Address Register
Performance Monitor Command Register
1
Total number of cycles since start bit was set
1
Total average read latency seen by EV5 (DECchip 21164)
Average latency for individual reads
1
Number of cycles for which system owned the add/cmd bus
1
Command Silo Register
1
Number of lock commands acknowledged
1
Number of memory barriers acknowledged
1
Number of set Dirtys issued by DECchip 21164
1
Number of those set Dirtys that were acknowledged
1
Number of CSR read commands
1
Number of memory space read miss commands
1
Number of read miss mod commands
1
Number of read miss STxC commands
1
Number of B-cache victims
1
Number of CSR write commands
1
Number of write block commands acknowledged
1
Number of write block lock commands acknowledged
1
Number of invalidates from system
1
Number of set Shared bits from system
1
Number of read Dirty bits from system
1
Address Silo Register
1
BB+1000
BB+1040
BB+1080
BB+10C0
BB+1200
BB+1240
BB+1280
BB+12C0
BB+1300
BB+1340
BB+1380
BB+13C0
BB+1400
BB+1440
BB+1500
BB+1540
BB+1580
BB+15C0
BB+1600
BB+1680
BB+16C0
BB+1800
BB+1840
BB+1880
BB+18C0
BB+1900
BB+1940
BB+1980
BB+19C0
BB+1A00
BB+1A40
BB+1A80
BB+1AC0
BB+1B00
BB+1B40
BB+1B80
BB+1BC0
BB+1C00
BB+1C40
BB+1C80
BB+1CC0
BB+1D00
BB+1D40
1
This register is used by performance analysts to monitor the overall performance of the CPU module.