Specifications

System Registers 7-43
TLMCR—Memory Control Register
Table 7-19 TLMCR Register Bit Definitions
A
ddress
A
ccess
BSB + 1880
W
The TLMCR register is used by memory nodes to set DRAM timing
rates. DRAM timing is dependent on bus cycle time and must be
written into each memory node to ensure the most efficient mem-
ory operation. DRAM timing affects the memory’s refresh rate. To
allow memory nodes to refresh simultaneously, this register sets
DRAM timing in all memory nodes in the system.
31 4
3
50
RSVD
DTR RSVD
BXB-0760-93
6
Name Bit(s) Type Function
RSVD
<31:6> W, 0 Reserved. Must be zero.
DTR
<5:4> W, 0 DRAM Timing Rate. Contents of this field are
memory node implementation specific.
RSVD
<3:0> W, 0 Reserved. Must be zero.