Specifications

7-40 System Registers

TLRMDQR8—Memory Channel Decr Queue Counter

ddress

ccess

BSB + 0640

R/W

The TLRMDQR register 8 is used by an I/O node to inform all node

when a Memory Channel address register becomes available. An

I/O port in physical node 8 issues writes to this register. If the I/O

node acknowledges the CSR write command, it must cycle the dat

bus and provide data with good ECC. The data is considered Un-

predictable and is not used by the receiver. The receiving nodes

must decrement the counter whether the command is acknowl-

edged or not.

31 0

BXB-0541V-93

Unpredictable