Specifications

System Registers 7-39

TLRMDQRX—Memory Channel Decr Queue Counter

ddress

ccess

BSB + 0600

R/W

The TLRMDQR register X is used by an I/O node to inform all

nodes when a Memory Channel address register becomes avail-

able. One I/O port in physical nodes 4 through 7 that is enabled to

handle Memory Channel transactions issues writes to this register

If the I/O node acknowledges the CSR write command, it must cy-

cle the data bus and provide data with good ECC. The data is con

sidered Unpredictable and is not used by the receiver. The receiv

ing nodes must decrement the counter whether the command is

acknowledged or not.

31 0

BXB-0541V-93

Unpredictable