Specifications

7-36 System Registers
TLIOINTRn—I/O Interrupt Registers
Table 7-17 TLI/OINTR Register Bit Definitions
To post an interrupt, the I/O port writes the TLI/OINTR register appropri-
ate for its node with the desired IPL(s) and the targeted CPUs.
These registers appear in TLSB broadcast space. Writes that address
these locations are accepted without regard to receiver node ID. This
A
ddress
A
ccess
BSB + 0100 through 0200
W
The TLIOINTRn registers are used by the I/O nodes to signal inter
-
rupts from the TLSB I/O system to processors.
31 16 15 0
VID_MASK
BXB-0498-93
RSVD
20 19 18 17
IPL 14 INTR
IPL 15 INTR 
IPL 16 INTR
IPL 17 INTR
Name Bit(s) Type Function
RSVD
<31:20> R/W, 0 Reserved. Must be zero.
INTL
<19:16> W1S, 0 Interrupt Level. When a bit is set in this field,
an interrupt is posted at the corresponding level.
INTL Bit IPL
<19>
<18>
<17>
<16>
17
16
15
14
VID_MASK
<15:0> W1S, 0 Virtual ID Mask. When a bit is set in this field,
an interrupt is posted in a corresponding CPU.
Specific CPUs are selected by virtual ID.