Specifications

System Registers 7-35

TLIPINTR—Interprocessor Interrupt Register

Table 7-16 TLIPINTR Register Bit Definitions

To post an interprocessor interrupt to another processor, a processor sets

the relevant bit in the TLIPINTR register. The bits are write one to set.

An interprocessor interrupt can be cleared by writing <IP_INTR> in the

appropriate TLINTRSUM register.

ddress

ccess

BSB + 0040

The TLIPINTR register is used by CPU nodes to signal inter-

processor interrupts.

31 16 15 0

MASK

BXB-0497-93

RSVD

Name Bit(s) Type Function

RSVD

<31:16> W, 0 Reserved. Must be zero.

MASK

<15:0> W1S, 0 Interprocessor Interrupt Mask. When a given

bit is set, an interprocessor interrupt is posted to

the corresponding CPU. Bit <0> posts an inter-

rupt to the CPU with VID0, bit <1> posts an inter-

rupt to the CPU with VID1, and so on. A bit in the

<MASK> field is cleared by a write to the appropri-

ate TLINTRSUM<IP_INTR>.