Specifications

7-32 System Registers
TLMBPR—Mailbox Pointer Registers
Table 7-14 TLMBPR Register Bit Definitions
Figure 7-1 shows the mailbox data structure.
A
ddress
A
ccess
BB + 0C00
W
The TLMBPR register posts mailbox requests in an I/O port for ac
-
cess to a CSR on an external I/O bus. Software access to this regis
-
ter is through the single address BB+0C00. CPU hardware selects
one of the 16 registers by asserting the value of the CPU’s virtual
ID on TLSB_BANK_NUM<3:0>.
0
0
0
5
0
6
3
9
4
0
6
3
MBZMBX_ADR <39:6>
BXB-0499-93
RSVD
Name Bit(s) Type Function
RSVD
MBX_ADR
<63:40>
<39:6>
W, 0
W, 0
Reserved. Must be zero.
Mailbox Address. Contains the 64-byte aligned
physical address of the mailbox data structure in
memory where the I/O port can find information to
complete the required operation.
MBZ
<5:0> W, 0 Reserved. Must be zero.