Specifications

7-30 System Registers

TLILIDn—Interrupt Level IDENT Registers

Table 7-12 TLILIDn Register Bit Definitions

NOTE: An internally generated I/O port error interrupt takes priority over device

interrupts. A read of TLILID3 returns the IDENT for an internal error be-

fore all pending device interrupt IDENTs.

ddress

ccess

BB + 0A00 through 0AC0

R/W

Each of the four TLILIDn registers is the topmost (oldest) entry in

a queue of the interrupts for that IPL. A read from this register

sends the "oldest" interrupt IDENT to the CPU that requests it.

When all active interrupts have been read, the TLILIDn register

returns zeros. This forces a passive release at the processor.

31 16 15 0

RSVD IDENT <15:0>

BXB-0495-93

Name Bit(s) Type Function

RSVD

<31:16> R/W, 0 Reserved. Must be zero.

IDENT

<15:0> R/W, 0 Identification Vector. The offset vector supplied

by the original I/O device/adapter that posted the

interrupt.