Specifications

7-26 System Registers
TLESRn—Error Syndrome Registers
Table 7-11 TLESRn Register Bit Definitions
A
ddress
A
ccess
BB + 0680 through 0740
R/W
The TLESRn registers contain the status information on a data er
-
ror within a 64-bit slice of the data.
TLESR0 contains the error syndrome and status derived from
TLSB_D<63:0>, TLSB_ECC<7:0>, and TLSB_DATA_VALID<0>.
TLESR1 contains the error syndrome and status derived from
TLSB_D<127:64>, TLSB_ECC<15:8>, and TLSB_DATA_VALID<1>.
TLESR2 contains the error syndrome and status derived from
TLSB_D<191:128>, TLSB_ECC<23:16>, and TLSB_DATA_VALID<2>
.
TLESR3 contains the error syndrome and status derived from
TLSB_D<255:192>, TLSB_ECC<31:24>, and TLSB_DATA_VALID<3>
.
31 30 22 21 20 19 18 17 16 15 087
RSVD SYND1 SYND0
BXB-0784C-94
TDE: Transmitter During Error
TCE: Transmitter Check Error
CPU and I/O: DVTCE; MEM: RSVD
UECC: Uncorrectable ECC Error
CRECC: Correctable
Read ECC Error 
CWECC: Correctable
Write ECC Error
LOFSYN

23
CPU1
 CPU0

24
Name Bit(s) Type Function
LOFSYN
<31> R/W, 0 Lock on First Syndrome. When set, the TLESR
register locks on the first error.
RSVD
<30:24> R/W, 0 Reserved. Must be written as zero.