Specifications

7-22 System Registers
Table 7-7 TLMMRn Register Bit Definitions (Continued)
Table 7-8 Interleave Field Values for Two-Bank Memory Modules
Name Bit(s) Type Function
INTLV
<10:8> CPU, W, 0
I/O, R/W, 0
Interleave. Lower address bits used in inter-
leaving. This field is compared to physical ad-
dress lines TLSB_ADR<8:6>. Table 7-8 gives
<INTLV> values for various interleave levels.
ADRMASK
<7:4> CPU, W, 0
I/O, R/W, 0
Address Mask. Indicates the number of ad-
dress bits not used in the address comparison.
This field allows physical memory sizes from 64
Mbytes through 1 terabyte to be mapped. Ad-
dress ranges indicated by various values of
<ADRMASK> are given in Table 7-9.
RSVD
<3:2> CPU, W, 0
I/O, R/W, 0
Reserved. Must be written as zero.
INTMASK
<1:0> CPU, W, 0
I/O, R/W, 0
Interleave Mask. Indicates how many bits are
valid in the interleave field. This permits 1, 2, 4,
and 8-way interleaving when <SBANK> is set,
or 2, 4, 8, and 16-way interleaving when
<SBANK> is clear. Table 7-8 gives <INTMASK>
values for various interleave levels.
Interleave
Level
Modules
Interleaved <SBANK> <INTMASK> <INTLV> Bank n Bank n+8
2-way
4-way
8-way
16-way
1
2
4
8
0
0
0
0
0
1
2
3
N/A
0:1
0:3
0:7
ADR<6>=0
ADR<7>=0
ADR<8>=0
ADR<9>=0
ADR<6>=1
ADR<7>=1
ADR<8>=1
ADR<9>=1