Specifications

1-4 Overview
to the DECchip 21164 Functional Specification for a complete description
of the DECchip 21164 and PALcode.
1.3.2 Backup Cache
Each backup cache (B-cache) is four Mbytes in size. In a dual-processor
module there are two independent backup caches, one for each CPU. Each
B-cache is physically addressed, direct-mapped with a 64-byte block and
fill size. The B-cache is under the direct control of the DECchip 21164.
The B-cache conforms to the conditional write-update cache coherency pro-
tocol as defined in the TurboLaser System Bus Specification.
The CPU module contains a duplicate copy of each B-cache tag store used
to maintain systemwide cache coherency. The module checks the duplicate
tag store on every TLSB transaction and communicates any required
changes in B-cache state to the DECchip 21164.
The CPU module also maintains a victim buffer for each B-cache. When
the DECchip 21164 evicts a cache block from the B-cache, the victim buffer
holds it. The DECchip 21164 writes the block to memory as soon as possi-
ble.
1.3.3 TLSB Interface
The CPU module uses six gate arrays to interface to the TLSB. The MMG
gate array orders requests from both DECchip 21164 processors. The ADG
gate array contains the TLSB interface control logic. It handles TLSB arbi-
tration and control, monitors TLSB transactions, and schedules data move-
ments with either processor as necessary to maintain cache coherency.
Four identical DIGA gate arrays interface between the 256-bit TLSB data
bus and the 128-bit DECchip 21164 processors. See Chapter 3 for brief
discussions of the gate arrays.
1.3.4 Console Support Hardware
The CPU module console support hardware consists of:
• Two Mbytes of flash EEPROM used to store console and diagnostics
software. A portion of this EEPROM is used to store module and sys-
tem parameters and error log information.
• One UART used to communicate with the user and power supplies.
• Battery-powered time-of-year (TOY) clock.
• One green LED to indicate CPU module self-test status.
• A second console UART for each processor, for engineering and manu-
facturing debug use.
An 8-bit Gbus, controlled by the ADG gate array, is provided to access the
console support hardware.
1.4 Memory Module
Memory modules are available in the following sizes: 128 Mbytes, 256
Mbytes, 512 Mbytes, 1 Gbyte, and 2 Gbytes. Sizes up to 1 Gbyte are sup-