Specifications

System Registers 7-21
TLMMRn—Memory Mapping Registers
Table 7-7 TLMMRn Register Bit Definitions
A
ddress
A
ccess
BB + 0200 to BB + 03C0
W (CPU), R/W (I/O)
The TLMMRn registers contain the mapping information for per-
forming bank decode.
31 3012
ADDRESS
BXB-0757-93
SBANK

INTMASK
4
6
5
7891030
ADRMSK
VALID
RSVD
25
INTLV
11
26
RSVD
12
Name Bit(s) Type Function
VALID
<31> CPU, W, 0
I/O, R/W, 0
Valid. When set, indicates that the mapping
register is valid and can be used in address de-
coding. <VALID> is set only if a corresponding
memory bank ID has been written to a memory
controller.
RSVD
<30:26> CPU, W, 0
I/O, R/W, 0
Reserved. Must be written as zero.
ADDRESS
<25:12> CPU, W, 0
I/O, R/W, 0
Address. Bank address range to be decoded.
This field is compared to the physical address
lines TLSB_ADR<39:26>.
SBANK
<11> CPU, W, 0
I/O, R/W, 0
Single Bank. Set to define a single bank num-
ber determined by the register number n.
Cleared to define two bank numbers, n and n+8.
This bit should be set when defining a bank
number for a single-bank module.