Specifications

7-20 System Registers
Table 7-6 TLVID Register Bit Definitions
Name Bit(s) Type Function
RSVD
<31:8> R/W, 0 Reserved. Must be written as zero.
VID_B
<7:4> R/W, 0 Virtual ID B. Contains the virtual ID for unit
B in this node. Reads zero if unimplemented.
CPU: Contains the virtual ID for CPU1. Initial-
izes to TLSB_NID<2:0> shifted left filled with
one. A read of this register reads the hardwired
value. However, the register must be written to
update the DIGA VID field.
Memory: Contains the virtual ID number for
memory bank 1. Console loads this field at in-
itialization time. The contents of this register are
compared to TLSB_BANK_NUM<3:0> during a
memory space command/address cycle to deter-
mine if bank 1 of this module is selected.
VID_A
<3:0> R/W, 0 Virtual ID A. Contains the virtual ID for unit
A in this node.
CPU: Contains the virtual ID for CPU0. Initial-
izes to TLSB_NID<2:0> shifted left filled with
zero. A read of this register reads the hardwired
value. However, the register must be written to
update the DIGA VID field.
Memory: Contains the virtual ID number for
memory bank 0. Console loads this field at in-
itialization time. The contents of this register are
compared to TLSB_BANK_NUM<3:0> during a
memory space command/address cycle to deter-
mine if bank 0 of this module is selected.