Specifications

System Registers 7-15
Table 7-5 TLCNR Register Bit Definitions
Name Bit(s) Type Function
LOFE
<31> R/W, 0 Lock on First Error. If set, the node locks the
TLBER and TLFADR registers when the first er-
ror bit is set in the TLBER register.
NRST
<30> W, 0 Node Reset. When set, the node undergoes a
reset sequence. The behavior of a node during
reset is implementation specific.
CPU: Starts self-test. Caches and CSRs are in-
itialized.
Memory: Self-test halts if running and does not
restart.
I/O: All logic except TLSB interface logic is re-
set. All internal registers are reset to their de-
fault values. Conditionally, attached I/O bus
adapters are reset through the hose signal, DN-
RST<3:0>, if DPDRn<DIS_DN_HOSE_RESET>
is not set. If DPDRn<DIS_DN_HOSE_RESET>
is set, the corresponding I/O bus adapter will not
be reset.
RSVD
<29:22> R/W, 0 Reserved. Read as zero.
RSTSTAT
<28> W1C, 0 Reset Status. Set when <NRST> is set.
Cleared by writing 1 to it, system power-up re-
set, or assertion of TLSB_RESET L.
RSVD
<27:22> R/W, 0 Reserved. Read as zero.
HALT_B
<21> R/W, 0 Halt CPU1. When set, CPU1 enters console
mode if the halt is enabled in the TLINTRMASK
register. Cleared by writing TLINTR-
SUM1<HALT> to zero.
Memory: Not implemented.
I/O: Not implemented.
HALT_A
<20> R/W, 0 Halt CPU0. When set, CPU0 enters console
mode if the halt is enabled in the TLINTRMASK
register. Cleared by writing TLINTR-
SUM0<HALT> to zero.
Memory: Not implemented.
I/O: Not implemented.
RSVD
<19:14> R0 Reserved. Read as zero.