Specifications

1-2 Overview
Futurebus+, or PCI bus. The local I/O options on the integrated I/O
port appear to software as a PCI bus connected to a hose.
Figure 1-1 shows a block diagram of the 8400 system.
Figure 1-1 AlphaServer 8400 System Block Diagram
1.2 Bus Architecture
The system bus, the TLSB, is a limited length, nonpended, pipelined syn-
chronous bus with separate 40-bit address and 256-bit data buses. The
TLSB supports a range of cycle times, from 10 to 30 ns. At 10 ns, the
maximum bandwidth available is 2.1 Gbytes/sec.
The TLSB runs synchronously with the CPU clock, and its cycle time is an
integer multiple of the CPU clock. Memory DRAM cycle time is not syn-
chronous with the TLSB clock. This permits memory access times to be
adjusted as the CPU clock is adjusted.
The TLSB supports nine nodes. One node (slot 8) is dedicated to I/O. This
node has special arbitration request lines that permit the node to always
arbitrate as the highest priority or the lowest priority device. This scheme
guarantees the node a maximum upper bound on memory latency. Any of
the other eight nodes can be a CPU or memory node. Four of these re-
maining nodes can be I/O ports.
Access to the address bus is controlled by a distributed arbitration scheme
implemented by all nodes on the bus. Access to the data bus is governed
by the order in which address bus transactions occur. Address and data



CPU,
MEM, or
I/O Module
CPU,
MEM, or
I/O Module
CPU,
MEM, or
I/O Module
CPU,
MEM, or
I/O Module
TLSB Bus; 40-bit address path, 256-bit data path
CPU or
MEM
Module
CPU or
MEM
Module
CPU or
MEM
Module
CPU or
MEM
Module
TLSB I/O
Port
Module
XMI
Interface
FBUS+
Interface
XMI
Interface
PCI
Interface
To/from XMI
To/from Futurebus+
To/from XMI
To/from PCI
BXB0813.AI