Specifications

I/O Port 6-81
Figure 6-35 Integrated I/O Section of the KFTIA
6.8.1.1 PCI Interface
The PCI interface provides a host bridge to two physical PCI buses. Each
bus operates at 33 MHz, and supports a 32-bit data path and 32-bit ad-
dress, for a raw bus bandwidth of 120 Mbytes/sec. The two buses appear
as physically separate, but share a common address space as viewed from
the host.
The integrated I/O port contains two hose to PCI bus interface gate arrays
(HPC). Each HPC controls one of the PCI buses. Down Hose 0 data from
the down HDR is sent to each of the HPCs in parallel. Up Hose data is
driven by each HPC on to the Up Hose 0 bus to the up HDR. Each HPC
arbitrates for the use of the Up Hose when sending packets over the Up
Hose or accessing the scatter/gather map RAM. Each HPC receives inter-
rupts from the embedded I/O devices, which it prioritizes and sends to the
TLSB bus interface section. Each HPC monitors Up Hose transactions to
maintain a consistent count of the number of transactions that the inte-
grated I/O section has outstanding.
HPC 1

QLogic
ISP 1020
DC287

HPC 0

Control 
and
Map RAM
NVRAM
Card
QLogic
ISP 1020
PCI 1
PCI 0
PCI 0
PCI 1
BXB0792.AI
Hose
Interface
Down
Up
10BaseT
FNS
FWD
Ethernet 1
SCSI 3
SCSI 2
FDDI
Card

QLogic
ISP 1020
Multimode
FWD
Ethernet 0
SCSI 1
FWD
SCSI 0
QLogic
ISP 1020
DC287

10BaseT
or UTP
FDDI