Specifications

I/O Port 6-71
The I/O port assertion checks TLSB_CMD_ACK only when it is being as-
serted by the the I/O port. If the I/O port detects a mismatch, it sets
<ACKTCE> and asserts TLSB_FAULT.
The I/O port assertion checks TLSB_ARB_SUP only when it is being as-
serted by the I/O port. If the I/O port detects a mismatch, it sets <AB-
TCE> and asserts TLSB_FAULT.
6.7.7.2 Address Bus Parity Errors
The I/O port monitors the address bus command, bank number, and ad-
dress fields for correct parity during valid transactions. If a parity error is
detected by the I/O port, the I/O port sets TLBER<APE>, latches the re-
ceived command, address and bank number information in the TLFADRn
registers, and asserts TLSB_FAULT. If the I/O port was the transmitter
during the error, <ATDE> is also set.
The state of the address bus fields during idle bus cycles is Undefined; par-
ity checking during those cycles is disabled.
6.7.7.3 No Acknowledge Errors
Two cycles after transmitting a regular command (not a no-op) on the
TLSB, the I/O port expects TLSB_CMD_ACK. If TLSB_CMD_ACK is not
received for a memory transaction, the I/O port sets TLBER<FNAE> and
asserts TLSB_FAULT. If TLSB_CMD_ACK is not received for a CSR
transaction, the I/O port sets TLBER<NAE> and posts an IPL 17 interrupt
to report the error. In addition to setting <NAE>, the I/O port transmits a
TLSB hard error code across its internal command bus to each IDR, effec-
tively aborting the transaction.
6.7.7.4 Unexpected Acknowledge
The I/O port monitors TLSB_CMD_ACK every cycle and sets <UACKE> if
it detects TLSB_CMD_ACK asserted when not expected. The I/O port also
asserts TLSB_FAULT on this error.
The I/O port only expects TLSB_CMD_ACK two cycles after a nonno-op
command is driven onto the TLSB. An unexpected acknowledge condition
is detected when TLSB_CMD_ACK is asserted and two cycles before was
either a no-op command or an idle cycle.
6.7.7.5 Bank Busy Violation
If the I/O port decodes a CSR command (to any address) while a CSR com-
mand is in progress, it sets its TLBER<BAE> and asserts TLSB_FAULT.
Additionally, the I/O port latches the address, command, and bank number
in its TLFADRn registers. If the I/O port was the transmitter during the
error, <ATDE> is also set.
6.7.7.6 Memory Mapping Register Error
The I/O port translates a memory address to a bank number before issuing
a command. This translation is performed by examining the contents of
its TLMMRn registers. The I/O port sets its TLBER<MMRE> if it cannot
determine a bank number from the memory address. If this error is de-