Specifications
6-60 I/O Port
Table 6-31 DMA Unmasked Write Packet Description
ADR<39:0> is the target address for the memory write and must be natu-
rally aligned to a double hexword boundary.
INTR/IDENT
The INTR/IDENT packet is the combined IDENT vector and IPL for an in-
terrupt on the I/O bus. The status of the interrupt transaction on the
TLSB bus is returned on the Down Hose with a INTR/IDENT Status Re-
turn packet.
This packet is supported by the Mailbox Only, I/O Window, Full, and Mem-
ory Channel variants of the hose protocol. Figure 6-29 shows the
INTR/IDENT Status Return packet.
Figure 6-29 INTR/IDENT Status Return Packet
Table 6-32 gives the description of the INTR/IDENT Status Return packet.
Field Description
Clock 1, <31:24>
Don’t Care. These bits, which normally form the TAG field, are don’t
care, since DMA Unmasked Write packets are disconnected and have no
corresponding return packet.
Clock 1, <23:11>
Are always zero.
Clock 1, <10:8>
The length field indicates the length of the packet. It must have the
value of 100 (double hexword).
Note: The DMA Unmasked Write packet is the most efficient DMA write
because it only requires a single write on the TLSB bus, whereas a DMA
Masked Write packet requires a Read-Modify-Write operation. Generally
speaking, an I/O bus adapter should be able to exploit the DMA Un-
masked Write packet whenever an I/O device is using a More type proto-
col.
Clock 1, <7:0>
ADR<39:32> of the target address. See definition below.
Clock 2, <31:0>
ADR<31:0> of the target address. See definition below.
Clocks 3 through 18
Data. One longword on each clock.
31 24 23 16 15 0
xxxx 0 0 0 IPL Vector <15 :0>
BXB-0647-93
UPD <31:0>
1*
2
* = Clock cycle
0
Don't Care
30
1000
UPCTL
xxxx
20 19