Specifications

6-56 I/O Port
Figure 6-26 Interlock Read Packet
Table 6-27 gives the description of the IREAD packet.
Table 6-27 Interlock Read Packet Description
ADR<39:0> is the target address for the TLSB memory read. It must be
naturally aligned to length (LEN) code of the data being requested.
NOTE: All IREADs must be naturally aligned quadwords. Therefore, the I/O port
ignores the length field and treats it as a quadword whenever it receives an
IREAD command on the Up Hose.
Table 6-28 Interlock Read Packet Size
31 24 23 11 10 087
TAG<7:0> 0 LEN ADR <39:32>
BXB-0640-93
ADR <31:0>
30
0010
UPD <31:0>
UPCTL
xxxx
1*

2
* = hose cycle
Field Description
Clock 1, <31:24>
The TAG<7:0> field allows the subsequent DMA Read Data Return packet
on the Down Hose to be associated with an IREAD packet on the Up Hose.
The tag is generated by the I/O bus adapter.
Clock 1, <23:11>
Are always zero.
Clock 1, <10:8>
The length field indicates the length of the DMA Read packet. The packet
data length of an IREAD packet is always an octaword and the length code
for the octaword packet indicates that only a quadword of data is re-
quested. This length code is looped back through the DMA Read Data Re-
turn packet and allows the I/O bus adapter to use the length code to ex-
tract the correct quadword from the octaword DMA Read Data Return
packet. See Table 6-28 for the IREAD packet size.
NOTE: All IREADs from the XMI must be naturally aligned quadwords.
Therefore, the I/O port ignores the length field and assumes a quadword
length whenever it receives an IREAD command on the Up Hose.
Clock 1, <7:0>
ADR<39:32> of the target address. See definition below.
Clock 2, <31:0>
ADR<31:0> of the target address. See definition below.
Length
Code
Packet Data
Length
Significant
Address Bits
1
Data
Requested
010
Octaword ADR<39:3> Quadword
1
ADR<2:0> are ignored by the I/O port.