Specifications

I/O Port 6-51
Table 6-22 Dense Window Write Command Packet Description
Figure 6-22 Byte Mask Field
Memory Chanel Write Packet
The Memory Channel Write packet is used by the I/O port to reflect a
TLSB memory space write to the remote I/O bus. When the hose is in nor-
mal mode, a Memory Channel Write packet must be acknowledged by a
Window Write Status Return packet (see Figure 6-22) to the I/O port on
the Up Hose. The Memory Channel Write packet is shown in Figure 6-23.
Field Description
Clock 1, <31:30>
Are always zero.
Clock 1, <29:26>
Virtual ID of the TLSB commanding node. The VID indicates which CPU
is requesting the data. The VID is returned on the Up Hose in all window
return data/status packets so that the I/O port can target the requesting
commanding node with the data or status of the transaction.
Clock 1, <25:15>
Are always zero.
Clock 1, <14>
Indicates read/write: 0 is read, 1 is write. For this packet bit <14> is al-
ways one.
Clock 1, <13:12>
Command field. The field value is 11 for all window command packets.
Clock 1, <11:2>
Are always zero.
Clock 1, <1:0>
SPC<1:0> field. The space field indicates which PCI address space is in
use as follows:
SPC<1:0> PCI Address Space
00
01
10
11
Dense memory space
Sparse memory space (not used with this packet)
Sparse I/O space (not used with this packet)
Sparse configuration space (not used with this packet)
Clock 2, <31:0>
Byte aligned address for the targeted remote I/O adapter. Bits <31:27>
are always zero.
Clock 3, <31:0>
Data mask bits. The I/O port generates the byte mask bits from the valid
bits received on the second TLSB data cycle. The I/O port replicates each
longword valid bit it receives from the TLSB into 4-byte enables as shown
in Figure 6-22. All bytes of each valid longword will always be one.
Clock 4 through
11, <31:0>
Data longword 0 through 7, respectively, to be written to the targeted re-
mote I/O bus.
1111 1111 1111 1111 1111 1111 1111 1111
LW7 LW6 LW5 LW4 LW3 LW2 LW1 LW0
BXB0801.AI