Specifications

6-42 I/O Port
Table 6-15 Mailbox Command Packet Description
DMA Read Data Return Packet
The DMA Read Data Return packet returns data previously requested by
an Up Hose DMA read packet. Figure 6-15 shows the DMA Read Data
Return packet.
Figure 6-15 DMA Read Data Return Packet
Field Description
Clock 1, <31:14>
Command <31:14> is specific to the remote bus (for example, XMI or
Futurebus+) rather than the I/O port, and contains the remote bus opera-
tion. It can include fields such as read/write, address only, address width,
data width, and so on.
Clock 1, <13:12>
Command <13:12> bits are forced by the I/O port to indicate a mailbox com-
mand packet (for example, 10 bin).
Clock 1, <11:0>
Command<11:0> is specific to the remote bus (for example, XMI or
Futurebus+), rather than the I/O port, and contains the remote bus opera-
tion. It can include fields such as read/write, address only, address width,
data width, and so on.
Clock 2, <31:24>
The hose number indicates to which Down Hose the Mailbox Command
packet is transmitted.
Clock 2, <23:8>
These bits are always zero.
Clock 2, <7:0>
MASK. Provides the mask bits for the write data when the Mailbox Com-
mand packet is a write. For Mailbox Command packets that are reads, the
MASK and Write Data fields are Unpredictable.
Clock 3 through
4, <63:0>
Address <63:0> of the I/O target address field. The I/O address to be writ-
ten is located in the I/O target address fields. Sixty-four bits of address are
supported by the Down Hose. However, the I/O bus adapter may or may not
support this address range.
Clock 5 through
6, <63:0>
Write Data <63:0> of the Write Data Field. The Mailbox Command packet
supports a quadword data length write in the Write Data field, but the I/O
bus adapter module might elect to use only the lower longword (Write Data
<31:0>) if it only supports longword access to CSR space.
Clock 7 through
8, <63:0>
These bits are always zero.
31 24 23 22 13 12 11 10 087
TAG <7:0> E 0 0 0 0 0 0 0 0 0 0 1 0 LEN 0 0 0 0 0 0 0 0
BXB-0641-93
DND <31:0>
Clock cycle
14
LWDATA1 <31:0>
LWDATA2 <31:0>
LWDATA15 <31:0>
LWDATA16 <31:0>