Specifications

I/O Port 6-31
6.5.2.1 Node 8 I/O Port Arbitration Mode Selection
Several mode-selectable lockout avoidance algorithms are implemented to
guarantee that the node 8 I/O port will eventually allow other nodes to ac-
cess a given memory bank on the TLSB while allowing software to fine-
tune I/O performance. A commander node is deemed "locked out" if it can-
not access a given memory bank for a long period of time. The default
"minimum latency" mode guarantees correct TLSB operation with optimal
node 8 I/O port performance. Selection of the various arbitration modes is
made through the ICCMSR register.
Minimum Latency Mode
This mode allows an I/O port in node 8 to gain access to the TLSB as
quickly as possible. Minimum latency is obtained by normally using
TLSB_REQ8_HIGH to arbitrate for the TLSB bus and only toggling be-
tween TLSB_REQ8_HIGH and TLSB_REQ8_LOW when requesting back-
to-back transactions to the same bank. This guarantees that the I/O port
cannot cause a bank lockout while allowing the I/O port to arbitrate
mainly at TLSB_REQ8_HIGH.
There are 16 flops, one for each bank, that are used to determine if the I/O
port should arbitrate for the target bank at TLSB_REQ8_HIGH or
TLSB_REQ8_LOW. When the I/O port wins the bus for a given bank, it
toggles the corresponding flop so that the next arbitration for that bank
will be performed at the alternate request level.
If the I/O port loses arbitration, or if a potential request cycle for a given
bank is seen, the I/O port switches to TLSB_REQ8_HIGH. A potential re-
quest cycle is any TLSB cycle in which TLSB_ARB_SUP and TLSB_REQ8
_HIGH are deasserted, and TLSB_BANK_AVL<n> is asserted. Also, the
cycle is not an arbitration cycle. There will be a minimum of four cycles
before the I/O port switches to TLSB_REQ8_HIGH to allow the look-back-
two logic to resolve any "false" arbitrations that may have delayed a "real"
arbitration from getting the bus.
The I/O port always uses TLSB_REQ8_HIGH when arbitrating for the
Write Bank Unlock portion of a Read-Modify-Write operation. Figure 6-11
shows the flow for this arbitration.
The example timing diagram in Figure 6-12 shows the I/O port requesting
the TLSB for the second transaction of back-to-back transactions to the
same bank. Since the first transaction (not shown in the diagram) was re-
quested using TLSB_REQ8_HIGH, the second transaction is requested in
cycles 3–6 using TLSB_REQ8_LOW. If the I/O port has not won the bus
by cycle 7, it switches to TLSB_REQ8_HIGH.