Specifications

I/O Port 6-17
Table 6-3 Sparse Address Space Read Field Descriptions
6.4.2.2 Sparse Address Space Writes
Figure 6-5 illustrates the TLSB address bus protocol for sparse address
space writes. Table 6-4 describes the sparse address space write protocol.
The data appears on the first data cycle of the TLSB data bus. Four Valid
bits appear on the second cycle of the TLSB data bus, one for each
quadword, in the positions shown in Figure 6-6.
Field Description
TLSB_BANK_NUM<3:0>
TLSB_ADR<39>
TLSB_ADR<38:36>
TLSB_ADR<35:34>
TLSB_ADR<33:32>
TLSB_ADR<31:5>
TLSB_ADR<4:3>
TLSB_ADR<2:0>
Contains the TLSB commander virtual ID (VID).
Indicates the address is an I/O address space reference. It will al-
ways be a one if the reference is in I/O address space.
Defines the responder TLSB node as follows:
Defines the hose number within the I/O port that is being ad-
dressed.
The Space Select field. Defines the type of PCI I/O transaction. It
is transmitted on the hose as SPC<1:0>.
This field is the byte-aligned 128-Mbyte target address. It maps to
ADR<26:0> on the remote I/O target bus. ADR<31:27> on the re-
mote I/O target bus is transmitted on the hose as zero.
This field is the byte-length code that defines the size of the re-
quested block. The byte-length code is transmitted on the hose as
LEN<1:0>. Its decode is specific to the remote I/O bus adapter.
The three least significant bits of the address bus are always zero.
TLSB_ADR<38:36> Node Defined
0
1
2
3
4
Node 4 I/O window space
Node 5 I/O window space
Node 6 I/O window space
Node 7 I/O window space
Node 8 I/O window space
TLSB_ADR<33:32> Node Defined
1
2
3
Sparse memory space
Sparse I/O space
Sparse configuration space