Specifications

I/O Port 6-5
Table 6-1 I/O Port Transaction Types
6.3.1 Mailbox Transactions
Some systems provide access to CSRs on external I/O buses (I/O devices)
indirectly, through a mailbox structure built by the CPU in main memory.
The I/O port reads and writes to this data structure, which maps almost
directly to a hose packet. Two such external I/O buses are:
• XMI
• Futurebus+
When a CPU chip wants to read or write a CSR on one of the external I/O
buses, it builds a mailbox structure and loads the Mailbox Pointer Register
(TLMBPR) in the I/O port. This causes the I/O port to fetch the mailbox
structure from TLSB memory into the mailbox buffer and build a Mailbox
Command packet for transmission across one of the four Down Hoses.
There are four separate TLMBPR register pairs visible to the hardware.
This allows up to eight CPU chips to each have its own private TLMBPR
register. Each CPU chip can have up to two mailboxes pending at a given
time within its own TLMBPR register pair. Thus, each I/O port can have
up to eight Mailbox Command packets pending at a time in its TLMBPR
register pairs. However, the I/O port can process only one Mailbox Com-
mand packet at a time.
Transaction Initiator TLSB Commands Hose Packets
CSR read
CSR write
Window read
Window write
Mailbox
DMA read
DMA write
DMA IREAD
1
DMA masked
write
1
Device interrupt
Error interrupt
Extended
NVRAM write
CPU
CPU
CPU
CPU
CPU
I/O device
I/O device
I/O device
I/O device
I/O device
I/O port
CPU
CSR read
CSR write
CSR read, CSR write
CSR write
CSR write, read, write
Read
Write
Read Bank Lock,
Write Bank Unlock
Read Bank Lock,
Write Bank Unlock
CSR write, CSR read
CSR write, CSR read
CSR write
None - local I/O port registers
None - local I/O port registers
Window read cmd, win rd data ret
Window wr cmd, win wr status ret
Mailbox cmd, Mailbox status ret
DMA read, DMA read data return
DMA unmasked write
DMA IREAD, DMA read data ret
DMA masked write cmd
INTR/IDENT cmd, INTR/IDENT
status return
None - local to I/O port
Memory Channel write, window
write status return
1
Since DMA IREADs and DMA masked writes are not defined TLSB commands, the I/O port implements their equiva-
lent functionality using TLSB Read Bank Lock and Write Bank Unlock commands to perform atomic Read-Modify-
Write sequences. This allows the I/O port to emulate an IREAD or a masked write.