Specifications

6-2 I/O Port
The I/O port interfaces the TLSB bus to up to four different I/O buses
through separate I/O bus adapter modules. Digital provides three types of
I/O adapters:
• XMI bus adapter—DWLMA
• Futurebus+ adapter—DWLAA
• PCI bus adapter—DWLPA (EISA bus through a bridge on the PCI bus)
6.1 Configuration
Node 8 of the TLSB is dedicated to the I/O port. Nodes 4, 5, 6, and 7 can
also be configured for I/O. The I/O port at node 8 arbitrates for the TLSB
bus using a dedicated high/low priority protocol. The I/O port usually arbi-
trates for the TLSB at the highest priority. If the I/O port requests back-
to-back transactions to the same memory bank, however, it will arbitrate
the second transaction on the lowest priority. This guarantees that other
nodes will never be locked out from winning a specific memory bank.
I/O ports at nodes 4, 5, 6, or 7 arbitrate for the TLSB bus in the normal
distributed arbitration scheme as do all other nodes, except for node 8.
The I/O port at node 8 has the highest priority and, thus, the lowest la-
tency. Therefore, all latency-sensitive I/O devices should be connected to
the TLSB bus through this I/O port.
6.2 I/O Port Main Components
The I/O port contains nine gate arrays:
• Four IDRs (I/O data path chip)
• One ICR (I/O control chip)
• Four HDRs (hose to I/O data path chip)
The four IDRs are identical arrays. IDR-0 interfaces the low-order
quadword of the 256-bit TLSB data path to the I/O port. It also houses
some of the I/O port’s CSR registers. IDR-1, IDR-2, and IDR-3 interface
the second, third, and fourth quadwords, respectively, of the data path to
the I/O port. The IDR arrays also interface to the HDR arrays through the
internal Turbo Vortex bus (see Figure 6-2). The sole purpose of this bus is
to function as an interconnect between the IDRs, ICR, and the HDRs.
The ICR array houses the primary control logic for the TLSB interface. It
performs the following functions:
• Interface to the TLSB address and control signals
• Interface to the HDR array control signals through the Turbo Vortex
bus
• Control of the clocking of data through the IDR gate arrays
• Housing for many of the I/O port’s CSR registers
Although the four HDR arrays are identical, each array functions differ-
ently, depending on where it is installed on the module. Two HDR arrays
are required to interface to a hose. One of the HDR arrays functions as an
Up Hose interface for two hoses, and the other functions as a Down Hose
interface for the same two hoses.