Specifications

Memory Interface 5-17
Table 5-7 CSRCA Data Bus Master
For a read command, the selected chip drives the appropriate data on the
CSRCA bus. Each of the MDI chips receives the data and loads it into its
Merge register. On a read, when the loading of the Merge register is com-
plete, MDI0 transfers the data onto the TLSB. For a write command, the
data to be written is received by MDI0 from the TLSB and loaded into its
Merge register. MDI0 then drives the data onto the CSRCA bus. The data
is received by all chips but only deposited into a register by the selected
chip at the selected address. Note that this scenario is true also for a write
to MDI0 itself. As was the case with the CTL sequencer, the MDI se-
quencer issues a LD_EN timing signal used to qualify when the data is
valid on the CSRCA bus.
5.3.2.2 Merge Register
The MDI Merge register temporarily stores CSR data to be either read or
written. For a write command, the lower 32 bits of data from the TLSB
data transfer is written into the Merge register. This data is then posted
on the CSRCA bus by MDI0, one byte at a time. For a read command, the
chip containing the register to be read drives the contents of that register
onto the CSRCA bus, one byte at a time. Each of the four bytes is loaded
into the MDI Merge registers for transfer onto the TLSB bus by MDI0.
5.3.2.3 CSR Multiplexing
The MDI contains two MUXes used to multiplex the appropriate CSR data
onto the CSRCA bus during a CSR read of an internal register. One MUX
is used to select the register currently being read. The select for this MUX
is determined by the CSRCA address. The second MUX is used to select
the appropriate byte of the 32-bit register to be selected. This MUX is con-
trolled by the MDI CSR sequencer.
The MDI also uses MUXes for selecting which data is to be written into the
Merge register. For a write command, the lower data portion of the TLSB
data is to be written into the Merge register. For a read command, each
data byte received from the CSRCA bus is loaded into the appropriate por-
tion of the Merge register.
Chip Select Read/Write CSRCA Driver
1XX - CTL
011 - MDI3
010 - MDI2
001 - MDI1
000 - MDI0
1XX - CTL
011 - MDI3
010 - MDI2
001 - MDI1
000 - MDI0
Read
Read
Read
Read
Read
Write
Write
Write
Write
Write
CTL
MD13
MD12
MD11
MD10
MD10
MD10
MD10
MD10
MD130