Specifications
xiii
6-30 DMA Masked Write Packet Sizes .............................................................................. 6-58
6-31 DMA Unmasked Write Packet Description............................................................... 6-60
6-32 INTR/IDENT Status Return Packet Description......................................................6-61
6-33 Sparse Window Read Data Return Packet Description............................................ 6-62
6-34 Dense Window Read Data Return Packet Description ............................................. 6-63
6-35 Window Write Status Return Packet Description .................................................... 6-64
6-36 PCI 0 and PCI 1 Interrupt Priority............................................................................ 6-85
7-1 TLSB Node Space Base Addresses...............................................................................7-3
7-2 TLSB Registers ............................................................................................................. 7-4
7-3 TLDEV Register Bit Definitions ..................................................................................7-5
7-4 TLBER Register Bit Definitions...................................................................................7-8
7-5 TLCNR Register Bit Definitions ................................................................................ 7-15
7-6 TLVID Register Bit Definitions .................................................................................7-20
7-7 TLMMRn Register Bit Definitions............................................................................. 7-21
7-8 Interleave Field Values for Two-Bank Memory Modules .........................................7-22
7-9 Address Ranges Selected by ADRMASK Field Values .............................................7-23
7-10 TLFADRn Register Bit Definitions............................................................................ 7-24
7-11 TLESRn Register Bit Definitions...............................................................................7-26
7-12 TLILIDn Register Bit Definitions .............................................................................. 7-30
7-13 TLCPUMASK Register Bit Definitions .....................................................................7-31
7-14 TLMBPR Register Bit Definitions .............................................................................7-32
7-15 Mailbox Data Structure Description..........................................................................7-33
7-16 TLIPINTR Register Bit Definitions ...........................................................................7-35
7-17 TLI/OINTR Register Bit Definitions..........................................................................7-36
7-18 TLRDRD Register Bit Definitions..............................................................................7-41
7-19 TLMCR Register Bit Definitions................................................................................ 7-43
7-20 CPU Module Registers................................................................................................ 7-45
7-21 Gbus Registers ............................................................................................................ 7-46
7-22 TLDIAG Register Bit Definitions...............................................................................7-47
7-23 TLDTAGDATA Register Bit Definitions ...................................................................7-50
7-24 TLDTAGSTAT Register Bit Definitions ....................................................................7-51
7-25 TLMODCONFIG Register Bit Definitions ................................................................7-52
7-26 TLEPAERR Register Bit Definitions ......................................................................... 7-55
7-27 TLEPDERR Register Bit Definitions......................................................................... 7-58
7-28 TLEPMERR Register Bit Definitions ........................................................................ 7-60
7-29 TLEP_VMG Register Bit Definitions......................................................................... 7-62
7-30 TLEPDERR Register Bit Definitions......................................................................... 7-64
7-31 TLINTRSUM Register Bit Definitions ......................................................................7-66
7-32 Memory Channel Range Register Bit Definitions..................................................... 7-71
7-33 TLDMCMD Register Bit Definitions .........................................................................7-73
7-34 TLDMADRA Register Bit Definitions........................................................................7-75
7-35 TLDMADRB Register Bit Definitions........................................................................7-76
7-36 GBUS$WHAMI Register Bit Definitions...................................................................7-77
7-37 GBUS$MISCR Register Bit Definitions .................................................................... 7-80
7-38 GBUS$MISCW Register Bit Definitions ................................................................... 7-81
7-39 GBUS$SERNUM Register Bit Definitions................................................................7-83
7-40 Memory-Specific Registers .........................................................................................7-85
7-41 SECR Register Bit Definitions ...................................................................................7-86
7-42 MIR Register Bit Definitions......................................................................................7-88
7-43 MCR Register Bit Definitions.....................................................................................7-90
7-44 STAIR Register Bit Definitions..................................................................................7-93
7-45 STAIR Register Bit Correspondence of Memory Address Segments ....................... 7-94
7-46 STER Register Bit Definitions ................................................................................... 7-96
7-47 MER Register Bit Definitions.....................................................................................7-97
7-48 MDRA Register Bit Definitions.................................................................................. 7-98
7-49 MDRB Register Bit Definitions................................................................................ 7-102