Specifications

Memory Interface 5-15
The memory adapter supports TLSB broadcast writes to its MCR register
at address location BSB+1880 (byte address). This allows for the DRAM
timing rates, accessed through the MCR register to be written simultane-
ously, thereby ensuring simultaneous refresh of all memory modules.
Since the commander initiating the broadcast write issues both the
TLSB_CMD_ACK and TLSB_SEND_DATA for the transaction, this is the
only transaction for which the memory adapter may issue TLSB_HOLD.
A TLSB CSR access to an existent node but nonexistent, nonbroadcast reg-
ister is followed by a TLSB_CMD_ACK and TLSB_SEND_DATA sequence,
but no data is written to any internal CSR for writes and Unpredictable
data is returned for reads.
5.3.1.2 MAI CSR Sequencer
The MAI CSR sequencer is the control mechanism that sequences the CTL
chip through a CSR read or a CSR write. Upon receiving an indication
from the TLSM CSR control, the CSR sequencer issues the command cycle
onto the CSRCA bus for two cycles. During the second cycle, the
CSR_CMD timing signal is asserted indicating to the MDI chips that a
valid command is present on the CSRCA bus. The third cycle is a dead cy-
cle used for tristate overlap.
Table 5-6 CSRCA Addressing
The following nine cycles are used to transfer the appropriate data from
chip to chip. One of the chips drives the CSRCA bus, based on the com-
mand issued, and the other chips all receive. The CTL only drives data
Chip Register CSRCA Address
CTL
TLDEV
TLBER
TLCNR
TLVID
TLFADR0
TLFADR1
SECR
MIR
MCR
STAIR
STER
MER
MDRA
MDRB
0000
0001
0010
0011
0100
0101
1000
1001
1010
1011
1100
1101
1110
1111
MDIs
TLESR
STDERA
STDERB
STDERC
STDERD
STDERE
DDR
0000
1000
1001
1010
1011
1100
1101