Specifications

5-14 Memory Interface
• Multiplexing of local CTL CSRs and the data bytes within them
• Byte-wide parity generation and checking of the CSRCA bus
5.3.1.1 TLSB CSR Control
The TLSB CSR control monitors the TLSB bus for either a CSR read or a
CSR write command destined for that particular node. The TLSB CSR
TLSM sequences the TLSB bus by issuing the TLSB_CMD_ACK,
TLSB_SEND_DATA, and sequence number at the appropriate time. It is
similar to the memory bank state machines. There are two parallel decode
operations that take place during reception of a TLSB command cycle.
• Command decode—Decode the TLSB command for either CSR read or
CSR write command.
• Address decode—Decode the TLSB address to determine if the opera-
tion is for this particular node. Refer to Table 2-7 for the TLSB node
number base address assignments.
If a CSR read or CSR write command is decoded and the address decode
indicates that the request is for this TLSB node, then a CMD_ACK is sent
to the TLSB. At the same time the TLSB command and address informa-
tion is encoded into the CSRCA format for transmission to the MDI chips
and an indication is sent to the MAI CSR sequencer to start the operation.
Figure 5-3 and Table 5-6 summarize the CSRCA encoding information.
Figure 5-3 CSRCA Encoding
For a CSR write transaction, transmission of the TLSB_CMD_ACK to the
TLSB is followed by TLSB_SEND_DATA. After the TLSB hold period has
passed, the MAI CSR sequencer starts a write process. For a CSR read
transaction, the MAI CSR sequencer is started at the assertion of
TLSB_CMD_ACK and some number of cycles later the
TLSB_SEND_DATA signal is issued on the TLSB.
ADS AD2 AD1 AD0 RD CS2 CS1 CS0
7
4
32
0
<2:0> Chip Select
1XX - MAI
011 - MDI3
010 - MDI2
001 - MDI1
000 - MDI0
<3> Read/Write
0 - Write
1 - Read
<7:4> Register Address
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