Specifications

Memory Interface 5-13
in these bits. This field is undefined when either CRECC, CWECC, or
ECC is zero.
5.3 CSR Interface
The CSR interface, used to transfer the appropriate CSR information be-
tween the CTL and the four MDI chips consists of an 8-bit data bus with
parity and a command timing signal.
The CSR interface manages the transfer of control and status information
between the TLSB bus and the TLSB accessible memory module registers.
On the memory module itself, the CSR Command/Address (CSRCA) bus is
the communications channel on which CSR information is passed between
the memory address interface chip (CTL) and the four memory data inter-
face chips (MDI). The CTL chip initiates all commands to transfer the ap-
propriate MDI or CTL CSR information through the CSRCA bus. The 8-
bit CSRCA bus is a multiplexed bus. For CSR writes the MDI0 chip re-
ceives the data from the TLSB and distributes the data to the appropriate
chip. For CSR reads, the chip that contains the register to be read drives
the data on the CSRCA bus. The data is stored in the MDI0 chip for trans-
fer to the TLSB. Figure 5-2 shows the CSR interface context.
Figure 5-2 CSR Interface Context
5.3.1 CTL CSR Functions
Internally, the CTL chip consists of the following functional blocks that
take part in TLSB CSR read or write operations of the memory module:
• TLSB CSR control
• CTL CSR sequencer
Memory Data
Interface

(MDI)
0
TLSB Bus
BXB0806A.AI
Memory Address Interface
(MAI)

CMD0 CMD1 CSRCA CMD2 CMD3
Memory Data
Interface

(MDI)
2
Memory Data
Interface

(MDI)
1
Memory Data
Interface

(MDI)
3