Specifications

5-10 Memory Interface
Figure 5-1 64-Bit ECC Coding Scheme
The received write data is checked for ECC errors. Any detected error is
logged as appropriate in the TLESRn error register. No correction is made
even though a single-bit error is detected. The data is written to the
DRAMs such that each of the four bits stored in each DRAM is protected
by a different set of ECC bits. Thus, when a whole chip DRAM failure oc-
curs, the failure results in single-bit errors in four different quadwords
rather than one or more uncorrectable error(s).
5.2.2.3 CSR Write Data ECC Check
CSR data transfers are protected by the same ECC code as memory data
transfers. However, single-bit errors detected on CSR writes are not cor-
rected by the memory. The detection of any data error on CSR writes to
memory causes the write to be aborted and the error to be logged in the
MDI TLESR as an uncorrectable ECC error.
5.2.2.4 Forcing Write Errors for Diagnostics
The write data path includes the means of inverting any one of the re-
ceived data bits and/or any one of the received check bits. The inversion
takes place between the time the data is received from the TLSB and its
being written to memory. Thus, good data can be received from the TLSB
and written to memory with a single- or double-bit error forced. This cor-
ruption of write data occurs only when the TLSB write address matches
the address in the CTL MDRB register. It is controlled by the MDI DDR
register.
XOR S7
XOR S6
XOR S5
XOR S4





XNOR S3
XNOR S2
XOR S1
XOR S0

HEX
SYNDROME
6666
3210
0000
1111
1111
1100

0011
1010
0001
1011

7766
50DB


5555
9876
0000
1111
1111
0000

1000
0110-
0101
0100

6666
8742


5555
5432
1111
0000
0000
1111

1110
1001
0101
1101

9999
DB87


5544
1098
1111
0000
0000
1100

0011
1001
0111
0001

9988
42AF


4444
7654
1111
0000
1111
1100

0011
1010
0001
1011

BBAA
50DB


4444
3210
1111
0000
1111
0000

1000
0110
0101
0100

AAAA
8742


3333
9786
0000
1111
0000
1111

1110
1001
0101
1101

5555
DB87

3333
5432

0000
1111
1111
1100

0011
1001
0111
0001

5544
42AF


1111
9876
0000
0000
0000
1100

0011
1001
0111
1110

1100
53BE


1111
5432
0000
0000
1111
1100

0011
1010
0001
0100

3322
41CA


11
1098
0000
0000
1111
0000

1000
0110
0101
1011

2222
9653



7654
1111
1111
0000
1111

1110
1001
0101
0010

DDDD
CA98



3210
1111
1111
0000
1100

0011
1001
0111
1110

DDCC
53BE


CHECK
BITS
XOR S7
XOR S6
XOR S5
XOR S4






7654

1000
0100
0010
0001

0000
0000
0000
0000

8421
0000




3210
0000
0000
0000
0000

1000
0100
0010
0001

0000
8421


DATA
BITS
XNOR S3
XNOR S2
XOR S1
XOR S0

HEX
SYNDROME

3322
1098
1111
1111
1111
1100

0011
1010
0001
0100

FFEE
41CA


2222
7654
1111
1111
1111
0000

1000
0110
0101
1011

EEEE
9653


2222
3210
0000
0000
0000
1111

1110
1001
0101
0010

1111
CA96


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