Specifications

Memory Interface 5-9
5.2 Memory Data Interface
The memory data interface (MDI) is comprised of four chips connected to
the DRAM array on one side and to the TLSB bus on the other. The MDI
contains the following logic elements:
• Data path logic
• Write data input logic
• Read data output logic
• Error detection and correction logic
5.2.1 Data Path Logic
The MDI data path provides an interface between the TLSB data path and
the DRAM array tri-state bus. Its primary parts are a write path that re-
ceives data from the TLSB data path and transmits it onto the DRAM ar-
ray bus, and a read path that receives data from the DRAM array bus and
then transmits the data onto the TLSB data path. The integrity of the
data read from the DRAMs is checked by means of a single error correcting
double error detecting (SECDED) ECC code. Any detected error is logged
in CSRs.
The data path logic also provides a path to and from the CSRs. The path
from the TLSB to the CSRs includes ECC checking on received data while
the path from the CSRs to the TLSB includes check bit generation. The
error correcting code is the same as that used to protect memory data.
5.2.2 Write Data Input Logic
The write data input logic receives data from the TLSB and transmits it
onto the DRAM array bus at the appropriate time in the DRAM write cy-
cle. Temporary storage is provided for the received data, so that it can be
held long enough to satisfy the DRAM write cycle timing requirements. A
path is also provided to the CSR Merge Register.
5.2.2.1 Write Data Buffer
The write data buffer in each MDI consists of four 72-bit data storage ele-
ments. Each of these quadword data buffers consists of eight bytes of data
and eight associated ECC bits. These buffers must receive data from the
TLSB and hold it long enough for it to be driven onto the DRAM array bus
and written into the DRAMs. Since write data for the second memory
bank could be received as soon as three TLSB cycles after data for the first
bank, separate buffer latches must be provided for each bank.
5.2.2.2 Write Data Path ECC Algorithm
The data is stored in the DRAMS protected by the same ECC code that
was used to protect the data on the TLSB. Thus, ECC bits do not have to
be generated on the received data. However, address parity is incorpo-
rated into the ECC prior to the data being written. The data and ECC bits
are latched as received from the TLSB, modified to include address parity
and then written to the DRAMS. Figure 5-1 shows the details of the ECC
code.