Specifications

5-8 Memory Interface
Table 5-4 Eight Strings—512MB/2048MB Row/Column Address Bit Swapping
DRAM Type
No. of Banks
Interleaved
DRAM Address
4 Mbit
1 2 4 8
16 Mbit
1 2 4 8
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
Col_Adr<0>
Col_Adr<0>
Col_Adr<0>
Col_Adr<0>
Col_Adr<0>
Col_Adr<0>
Col_Adr<0>
Col_Adr<0>
Col_Adr<0>
Col_Adr<0>
Mod_Sel<0>
Mod_Sel<0>
Mod_Sel<0>
Bank_Sel<0>
Ras_Sel<0>
Ras_Sel<1>
7
8
9
10
11
12
13
14
15
16
x(21)
x(22)
21
22
3
4
5
6
17
18
19
20
x
x
x
1
2
3
7
8
9
10
11
12
13
14
15
16
x(21)
x(22)
21
22
23
24
5
6
17
18
19
20
1
x
x
2
3
4
7
8
9
10
11
12
13
14
15
16
x(21)
x(22)
21
22
23
24
25
6
17
18
19
20
1
2
x
3
4
5
7
8
9
10
11
12
13
14
15
16
x(21)
x(22)
21
22
23
24
25
26
17
18
19
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
21
22
23
24
25
4
5
6
17
18
19
20
x
x
x
1
2
3
7
8
9
10
11
12
13
14
15
16
21
22
23
24
25
26
5
6
17
18
19
20
1
x
x
2
3
4
7
8
9
10
11
12
13
14
15
16
21
22
23
24
25
26
27
6
17
18
19
20
1
2
x
3
4
5
7
8
9
10
11
12
13
14
15
16
21
22
23
24
25
26
27
28
17
18
19
20
1
2
3
4
5
6
Key to 4M DRAM Unused Row Addresses/Ras_Sel and Mod_Sel:
x(n) : Don’t Care. (n) is the address bit driven even though it is not used by the DRAMs.
x : Don’t Care. No address bits are involved in this decision.