Specifications

Memory Interface 5-7
Table 5-3 Four Strings—256MB/1024MB Row/Column Address Bit Swapping
5.1.3.3 512MB/2048MB Memory Module Addressing
Table 5-4 shows how the TLSB addresses are allocated for an eight-string
memory module. As shown, Ras_Sel<1:0> are now affected by addresses
since we need to select one of the four strings per bank.
DRAM Type
No. of Banks
Interleaved
DRAM Address
4 Mbit
1 2 4 8
16 Mbit
1 2 4 8
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
Row_Adr<0>
Col_Adr<0>
Col_Adr<0>
Col_Adr<0>
Col_Adr<0>
Col_Adr<0>
Col_Adr<0>
Col_Adr<0>
Col_Adr<0>
Col_Adr<0>
Col_Adr<0>
Mod_Sel<0>
Mod_Sel<0>
Mod_Sel<0>
Bank_Sel<0>
Ras_Sel<0>
Ras_Sel<1>
7
8
9
10
11
12
13
14
15
16
x(21)
x(22)
21
22
3
4
5
6
17
18
19
20
x
x
x
1
2
"0"
7
8
9
10
11
12
13
14
15
16
x(21)
x(22)
21
22
23
4
5
6
17
18
19
20
1
x
x
2
3
"0"
7
8
9
10
11
12
13
14
15
16
x(21)
x(22)
21
22
23
24
5
6
17
18
19
20
1
2
x
3
4
"0"
7
8
9
10
11
12
13
14
15
16
x(21)
x(22)
21
22
23
24
25
6
17
18
19
20
1
2
3
4
5
"0"
7
8
9
10
11
12
13
14
15
16
21
22
23
24
3
4
5
6
17
18
19
20
x
x
x
1
2
"0"
7
8
9
10
11
12
13
14
15
16
21
22
23
24
25
4
5
6
17
18
19
20
1
x
x
2
3
"0"
7
8
9
10
11
12
13
14
15
16
21
22
23
24
25
26
5
6
17
18
19
20
1
2
x
3
4
"0"
7
8
9
10
11
12
13
14
15
16
21
22
23
24
25
26
27
6
17
18
19
20
1
2
3
4
5
"0"
Key to 4M DRAM Unused Row Addresses/Ras_Sel and Mod_Sel:
x(n) : Don’t Care. (n) is the address bit driven even though it is not used by the DRAMs.
x : Don’t Care. No address bits are involved in this decision.
"0" : Always 0. This signal is always held deasserted.