Specifications

5-4 Memory Interface
received from the TLSB bus. TLSB_SEND_DATA is also used to check for
proper bus sequencing. Note that the TLSB_CMD_ACK and TLSB_SEND
_DATA may be issued simultaneously for write transactions by the mem-
ory module on an idle TLSB bus.
The CTL maintains sequence number registers for each memory bank as
well as for CSR transactions. Whenever a command/address request is re-
ceived, the corresponding address sequence number is stored in the regis-
ter allocated to the particular bank along with a valid bit. This tagged
value is used to identify the proper time slot for the return data to be is-
sued on the TLSB bus. Whenever the data bus sequencing register is equal
to a bank sequence register with the corresponding valid bit being set,
then the transaction requested of that bank is the next data to be returned
on the TLSB bus.
5.1.1.9 TLSB Bank Available Flags
The CTL has two bank available flags, one for each memory bank. De-
pending on the virtual ID of each bank, VID A and VID B in the TLVID
register, each of the bank available flags will correspond to one of the
TLSB BANK_AVL lines. If either of the bank available flags is clear, all
TLSB commander nodes are blocked from requesting a transaction from
that particular bank.
The bank available flag becomes clear in the same cycle the command re-
questing the transaction of that bank is acknowledged (CMD_ACK). The
bank available flag then remains clear until the memory module is able to
receive another command from the TLSB for that particular bank. For
memory write operations the DRAM control sequencer sets the appropriate
bank available flag. For memory read operations, excluding Read Bank
Lock, the state machine sets the appropriate bank available flag. The
bank available flag remains clear after the completion of a Read Bank
Lock command until the completion of a Write Bank Unlock to the same
memory bank. The Write Bank Unlock command may be requested on the
TLSB bus after the hold window for the return of read data for the Read
Lock command has passed.
5.1.2 DRAM Control
The DRAM array control and address generation is handled entirely
within the CTL chip. The only external components in the address/control
path to the DRAMs are buffers for fanout.
Then DRAM control structure consists of the following functional blocks:
• Bank 0 DRAM state machine (DSM0)
• Bank 1 DRAM state machine (DSM1)
• Address/RAS decode logic
The DRAM state machine is the controlling element for a bank (a bank of
memory is a group of 144, 288, or 576 DRAMs that share a common set of
row/column address resources from the CTL) of dynamic memory. As a
controller for DRAMs, it has three classes of operations to perform and a
unique control flow associated with each operation. These operations are:
• Read