Specifications

Memory Subsystem 4-19
NOTE: Successful execution is not a measure of the array integrity. It indicates that
every location in memory space has been tested and written with good or
bad ECC.
If node reset occurs during self-test, the array will be left in an unknown
state. Unlike TLSB reset, node reset does not initiate self-test.
4.3.6.4 Self-Test Performance
The memory module’s test time depends on the following parameters:
• DRAM size
• DRAM speed
• Memory array capacity
• Memory array architecture
• Clock speed
The self-test time is determined largely by the memory module’s capacity.
Tables 4-7 and 4-8 list the expected self-test times of various memory ca-
pacities based on a 10 ns bus clock. Test times during system power-up or
TLSB reset are directly proportional to bus clock speed, because the opti-
mum DRAM timing rate has not been loaded into the configuration regis-
ter yet. Therefore, modules installed in a system with a 15 ns clock would
take approximately 50 percent longer to test. If self-test is invoked with
CSR commands after the console has selected the timing rate, test times
should match the values given in Table 4-7 regardless of bus speed.
Table 4-7 Self-Test Times: Normal Mode
Module Capacity
(Mbytes)
Test Time (seconds)
4 Mbit DRAM 16 Mbit DRAM
128
256
512
1024
2048
.8
1.5
2.9
N/A
N/A
N/A
1
1.5
2.9
5.8
11.5
1
NA = Not applicable