Specifications

Memory Subsystem 4-17
sole to locate and map out bad areas of physical address space. Self-test is
invoked during system power-up, when a TLSB reset occurs, or by writing
to the appropriate CSRs.
Two versions of self-test are supported. A normal self-test that runs upon
power-up/reset and tests the module rapidly and completely with "pseudo-
random" data and address patterns. The test ensures detection of failures
prior to booting an operating system. In summary, pseudo-random self-
test leaves memory in the following states depending upon whether errors
were detected:
• No errors detected
— Memory initializes all locations with proper ECC.
— The STF bit(s) are cleared and the LED is lit.
• Errors detected
— Location(s) in error are written to an all ones pattern with
uncorrectable ECC errors in the check field bits.
— Error isolation information is logged into specific error registers.
— The STF bit(s) are cleared and the LED is lit.
The second version of self-test, which is selected through diagnostic CSR
writes, uses the moving inversion algorithm to detect DRAM sensitivity
problems. This test (normally run in manufacturing only) is used to isolate
DRAM sensitivity failures by using a test pattern (floating zeros) known to
detect this class of failures. It executes 50 times slower than normal self-
test due to the massive number of patterns and iterations that must be
performed on each memory location.
4.3.6.1 Self-Test Modes
Self-test can be executed in three modes selectable through the MDRA reg-
ister and the DDRn registers:
• Normal
• Pause on error (POEM)
• Free run (FRUN)
In a system environment, normal mode, test address and data patterns are
generated in a pseudo-random fashion accessing all of memory space using
the same primitive polynomials. TLSB self-test logic is partitioned into
five gate arrays and uses four 72-bit test pattern generators.
Within POEM and FRUN, address and data can be generated pseudo-
randomly, or with a moving inversion algorithm. Self-test Data Error reg-
isters (STDERn) in the MDI chips are used together with the Self-Test Er-
ror Register (STER) in the CTL to isolate down to the failing data bit dur-
ing POEM mode testing.
Unlike normal mode, which stops after testing the entire array and clears
the execute self-test bit, POEM and FRUN automatically loop on self-test
until the operator clears MDRA<EXST>. When this occurs, self-test con-
tinues until the current loop is complete.