Specifications

4-16 Memory Subsystem
group of DRAM arrays. The default mode optimizes interleaving of mem-
ory in any arrangement of memory modules.
If the FEPROM specifies explicit interleave sets, the console then inter-
leaves the arrays as requested. In a noninterleave mode, the console con-
figures arrays in order, by node number, with the lowest numbered array
at the lowest physical address.
4.3.3 Refresh
Each module implements CBR (CAS Before Ras) DRAM refresh. All mem-
ory modules refresh at the same time providing that a module is not servic-
ing a TLSB memory transaction at the time when a refresh is requested. If
a refresh request is asserted after a TLSB transaction has begun in a given
memory bank, the TLSB transaction is completed and is followed immedi-
ately by the refresh operation.
Module refresh is initiated under two different circumstances: power-up
and system reset. Upon the deassertion of TLSB_RESET, all array mod-
ules initiate a start-up procedure that consists of:
• At least eight DRAM refresh cycles to initialize the DRAMS.
• All CSRs and required internal logic are set to a known initialized
state.
• Self-test is initiated and run to completion.
4.3.4 Transactions
Memory responds to but cannot initiate TLSB transactions. It responds to
accesses to the memory space and to its own TLSB node space.
Memory modules run synchronously with the TLSB. Memory transfers
consist of two contiguous, 32-byte data cycles, for a total of 64 bytes per
transaction. Read and write data wrapping is supported on 32-byte natu-
rally aligned boundaries.
4.3.5 ECC Protection
During memory writes, memory modules store write data and ECC check
bits as they are received off the TLSB. A minor modification of the ECC
check bits is done before they are written to the DRAMs to allow for the
addition of a Row parity bit and a Col parity bit to provide additional data
integrity protection. During memory reads, memory modules strip off the
encoded Row/Col parity bits from the ECC check bits prior to asserting the
read data and check bits onto the TLSB.
Since x4 DRAMS are used, each of the 4 bits in a single DRAM is protected
by a different check bit field. This structure ensures that a single failing
DRAM is incapable of generating an uncorrectable ECC error.
4.3.6 Self-Test
Each module implements a built-in self-test to test the DRAM array and
initialize the DRAMs with good ECC. Self-test’s objectives during system
operation are to initialize the array into a known state and, by flagging
bad segments of memory, reduce the amount of time necessary for the con-