Specifications

xi
4-3 Cache Index and Tag Mapping to Block Address (16MB)...................................... 4-4
4-4 Memory Module Block Diagram ............................................................................ 4-10
4-5 Two-Way Interleave of a 128-Mbyte DRAM Array ..............................................4-14
4-6 Interleaving Different Size Memory Modules.......................................................4-14
4-7 Eight-Way System Interleave of Four 128-Mbyte Memory Modules .................. 4-15
5-1 64-Bit ECC Coding Scheme ................................................................................... 5-10
5-2 CSR Interface Context ...........................................................................................5-13
5-3 CSRCA Encoding....................................................................................................5-14
6-1 I/O Subsystem Block Diagram.................................................................................6-1
6-2 I/O Port Block Diagram............................................................................................ 6-3
6-3 Sparse Address Space Reads ................................................................................. 6-16
6-4 Sparse Window Read Data as Presented on the TLSB ........................................ 6-16
6-5 Sparse Address Space Writes ................................................................................ 6-18
6-6 Sparse Address Space Write Data......................................................................... 6-18
6-7 Dense Address Space Transactions....................................................................... 6-20
6-8 Dense Address Space Write Data.......................................................................... 6-22
6-9 Dense Window Read Data as Presented on the TLSB .........................................6-22
6-10 Write CSR (Interrupt) Data Format ...................................................................6-27
6-11 Minimum Latency Mode ......................................................................................6-32
6-12 Minimum Latency Mode Timing Example ......................................................... 6-32
6-13 Toggle 50% High/50% Low Mode.........................................................................6-33
6-14 Mailbox Command Packet ................................................................................... 6-41
6-15 DMA Read Data Return Packet .......................................................................... 6-42
6-16 DMA Read Data Return Packet with Error........................................................6-44
6-17 INTR/IDENT Status Return Packet ...................................................................6-45
6-18 Sparse Window Read Command Packet ............................................................. 6-45
6-19 Sparse Window Write Command Packet ............................................................ 6-47
6-20 Dense Window Read Command Packet ..............................................................6-48
6-21 Dense Window Write Command Packet .............................................................6-50
6-22 Byte Mask Field....................................................................................................6-51
6-23 Memory Channel Write Packet ...........................................................................6-52
6-24 Mailbox Status Return Packet.............................................................................6-53
6-25 DMA Read Packet ................................................................................................6-54
6-26 Interlock Read Packet ..........................................................................................6-56
6-27 DMA Masked Write Packet .................................................................................6-57
6-28 DMA Unmasked Write Packet ............................................................................ 6-59
6-29 INTR/IDENT Status Return Packet ...................................................................6-60
6-30 Sparse Window Read Data Return Packet ......................................................... 6-61
6-31 Dense Window Read Data Return Packet .......................................................... 6-63
6-32 Window Write Status Return Packet .................................................................. 6-64
6-33 KFTIA Connections ..............................................................................................6-78
6-34 KFTIA Block Diagram ......................................................................................... 6-79
6-35 Integrated I/O Section of the KFTIA...................................................................6-81
7-1 Mailbox Data Structure .........................................................................................7-33
Tables
1 Digital AlphaServer 8200/8400 Documentation......................................................... xvii
2 Related Documents ....................................................................................................... xix
2-1 TLSB Bus Signals ......................................................................................................... 2-3
2-2 TLSB Physical Node Identification..............................................................................2-5
2-3 Interleave Field Values for Two-Bank Memory Modules ...........................................2-9
2-4 TLSB Address Bus Commands ..................................................................................2-17
2-5 TLSB Data Wrapping ................................................................................................. 2-21
2-6 CSR Address Space Regions....................................................................................... 2-26