Specifications

Memory Subsystem 4-11
4.3.1.1 Control Address Interface
The control address interface (CTL) is a single gate array. It provides the
interface to the TLSB, controls DRAM timing and refresh, runs memory
self-test, and contains some of the TLSB and memory-specific registers.
CTL decodes the TLSB command and memory bank in the case of memory
reads and writes, or the TLSB address during CSR operations to deter-
mine if it is selected for this transaction. In addition, command/address
parity is checked to determine if a command/address parity error has oc-
curred.
CTL contains the TLSB control sequencers responsible for the TLSB proto-
col.
CTL provides separate copies of Row/Column address, RAS, CAS, and WE
signals for each of the two DRAM banks.
CTL controls the operation of the serial EEPROM on the memory module.
The EEPROM contains the following information:
• The serial number of the module. This is entered into the EEPROM by
manufacturing during module build.
• The module revision. This is entered into the EEPROM by manufac-
turing during module build. It is updated, as appropriate, anytime
the module’s revision changes.
• Self-test failures. If self-test fails, the console logs self-test failure data
in the EEPROM.
• Memory module error logging data. This information is used to help
diagnose and isolate failures on modules returned to a repair depot.
CTL interfaces to the TLSB command/address bus, which is independent
from the data bus.
Internally, CTL consists of the following major functional areas:
• TLSB interface logic—command/address decode
• DRAM address generation logic, bank 0
• DRAM address generation logic, bank 1
• DRAM control signal timing logic, bank 0
• DRAM control signal timing logic, bank 1
• DRAM refresh control logic for both banks
• CSRs
• Self-test address generation logic
• TLSB state machine control logic
• EEPROM control logic
• Control interface to the four MDI ASICs
4.3.1.2 Memory Data Interface
Each memory module has four memory data interface (MDI) ASICs. Each
MDI has a 72-bit interface to the TLSB and a 144-bit data interface to the