Specifications

4-10 Memory Subsystem
During memory writes, TLSB memory modules store write data and ECC
check bits as they are received off the TLSB. A minor modification of the
ECC check bits is done before they are written to the DRAMs to allow for
the addition of a row parity bit and a column parity bit to provide addi-
tional data integrity protection. During memory reads, memory modules
strip off the encoded Row/Col parity bits from the ECC check bits prior to
asserting the read data and check bits onto the TLSB.
4.3.1 Major Sections
A TLSB memory module consists of three major sections:
• Control address interface (CTL)
• Memory data interface (MDI)
• DRAM arrays
The major sections communicate with each other through internal buses.
Figure 4-4 shows a simple block diagram of a memory module.
Figure 4-4 Memory Module Block Diagram
Memory DRAM Bank 1
(144 DRAMs/string)
0 - 4 strings
Memory DRAM Bank 0
(144 DRAMs/string)
1 - 4 strings
MDI
3
MDI
2
CTL
MDI
1
MDI
0
TLSB Bus

D<575:432>
ADR
DRAM
Control

D<431:288>
D<287:144>
D<143:0>
Control/
Address
Buffers
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