Specifications

4-8 Memory Subsystem
Table 4-3 State Transition Due to TLSB Activity
Table 4-4 shows how the CPU module responds to bus activity directed at
these addresses that hit in the victim buffers or lock register.
Table 4-4 CPU Module Response to Lock Register and Victim Buffer Address Hits
4.2.9 Cache Coherency on Processor Writes
The DTag is selected as the CPU module point of coherency. This is done
because:
• The DTag is logically near to the TLSB.
• Only one activity can be scheduled through the DTag at a time.
• The correct response sequence to bus and module requests can be guar-
anteed.
When a DECchip 21164 wants to write a private, clean block in its S-
cache, it issues a Set Dirty request. This request sets the Dirty bit for that
cache line in the DTag, unless a bus access is currently in the internal se-
quencers that will transition the block to the shared state. In such a case
TLSB
Operation Tag Probe Result
1
Module
Response
Next Cache
State Comment
Read
Write
Read
Read
Write
_____
Match OR Invalid
_____
Match OR Invalid
_____
Match AND Dirty
Match AND Dirty
Match
______ _____
Shared, Dirty
______ _____
Shared, Dirty
_____
Shared, Dirty
Shared, Dirty
______ _____
Shared, Dirty
No change
No change
_____
Shared, Dirty
Shared, Dirty
Invalid
This module must
supply the data.
______
1
An overscore on a cache block status bit indicates the complement of the state. For example, Shared = Not Shared.
TLSB
Operation Address Matched Module Response Action
Read
Write
Read
Write
Lock register
Lock register
Victim buffer
Victim buffer
Shared, Dirty
______ _____
Shared, Dirty
Shared, Dirty
______ _____
Shared, Dirty
No action
Clear Lock bit, invalidate
Supply data from victim buffer
Invalidate victim buffer
______
1
An overscore on a cache block status bit indicates the complement of the state. For example, Shared = Not Shared.